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| author | Thibaut Girka <thib@sitedethib.com> | 2018-10-22 18:22:01 +0200 |
|---|---|---|
| committer | Thibaut Girka <thib@sitedethib.com> | 2018-10-22 18:22:01 +0200 |
| commit | bf9c4b6d98628dacdf5617d86611d4aafbc14921 (patch) | |
| tree | 4fe61f145526298ee57407842107759bb41d4e26 /app/controllers | |
| parent | 9f1c9b6135717535a48be0584dd777c9c8c34d76 (diff) | |
[Glitch] undo part of PR 8202 to fix RTL
Port efd09e2ebba7e9f0135bd47c44a77e2fc421aa67 to glitch-soc
Diffstat (limited to 'app/controllers')
0 files changed, 0 insertions, 0 deletions